(Note added Dec 12th, 2008) The PDFs of presentations from this seminar tour (and previous ones in the same series) are at the Agilent High Speed Seminar Presentation Page.
Agilent divisions, including my own EEsof division, are together offering a free seminar “High-Speed Digital Seminar - Tackling High-Speed Serial Designs” in six North American cities.
Locations/Dates:- Sept. 16, 2008 …….. Santa Clara, CA
- Sept. 23, 2008 …….. Austin, TX
- Sept. 25, 2008 …….. Richardson, TX
- Sept. 30, 2008 …….. Sunrise, FL
- Oct. 15, 2008 ………. Thornhill, ON
- Oct. 17, 2008 ………. Ottawa, ON
- 8:00 am - 8:30 am Registration & Continental Breakfast
- 8:30 am - 9:00 am Kickoff “Tackling High-Speed Serial Designs”
- 9:00 am - 10:00 am How to Solve DDR Parametric and Protocol Measurement Challenges
- 10:00 am - 10:15 am Break/Demo Fair
- 10:15 am - 11:15 am Successfully Negotiating The PCI Express 2.0 Super Highway Towards Full Compliance
- 11:15 am - 12:15 pm Characterizing Your PLL-based Designs To Manage System Jitter
- 12:15 pm - 1:15 pm Complimentary Lunch/Demo Fair
- 1:15 pm - 2:15 pm Modeling Multi-Gigabit FPGA Channels Using ADS
- 2:15 pm - 3:15 pm TDR, S-Parameters & Differential Measurements
- 3:15 pm - 4:15 pm A Design of Experiments for Gigabit Serial Backplane Channels
- 4:15 pm - 4:45 pm Demo Fair
- 8:00 am – 8:30 am Registration & Continental Breakfast
- 8:30 am – 9:00 am Kickoff “Tackling High-Speed Serial Designs”
- 9:00 am – 10:00 am How to Solve DDR Parametric and Protocol Measurement Challenges
- 10:00 am – 10:15 am Break/Demo Fair
- 10:15 am – 11:15 am Characterizing Your PLL-based Designs To Manage System Jitter
- 11:15 am – 12:15 pm Testing Certified Wireless USB and Wired USB Designs
- 12:15 pm – 1:15 pm Complimentary Lunch/Demo Fair
- 1:15 pm – 2:15 pm Optimize Mobile Device Run-time With Battery Drain Analysis Techniques
- 2:15 pm – 3:15 pm TDR, S-Parameters & Differential Measurements
- 3:15 pm – 4:15 pm Why Do Measurement-Based Channel Modeling?
- 4:15 pm – 4:45 pm Demo Fair
High-Speed Digital Seminar - Tackling High-Speed Serial Designs
Hope to see you there!
![[del.icio.us]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/delicious.png)
![[Digg]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/digg.png)
![[Facebook]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/facebook.png)
![[Google]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/google.png)
![[LinkedIn]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/linkedin.png)
![[Reddit]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/reddit.png)
![[Slashdot]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/slashdot.png)
![[StumbleUpon]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/stumbleupon.png)
![[Technorati]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/technorati.png)
![[Twitter]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/twitter.png)
![[Windows Live]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/windowslive.png)
![[Yahoo!]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/yahoo.png)
![[Email]](http://signal-integrity-tips.com/wp-content/plugins/bookmarkify/email.png)
1 response so far ↓
1 Eric Bogatin’s Blog: What I Learned This Month » 9/15/08 Really Cool Events Coming Your Way // Sep 15, 2008 at 4:32 pm
[...] Sept 16 - Oct 17, there is the “High-Speed Digital Seminar - Tackling High-Speed Serial Designs“. This is a series of presentations on SI issues, like DDR, PCIe, PLLs, Gbps FPGAs and VNA [...]
Leave a Comment