This puzzle appears to be a classic lossy ISI problem. We work with these all the time. So much so that we developed a line of high pass filters that are the inverse function of the typical bessel loss of a transmission line. We plot the S-parameters and mark the loss point of the fundamental frequency of the expected data rate. We then use a measured model of this filter part with the channel measurement to show the expected eye using this filter.

ADS schematics and resulting eye diagram

This is very easy and took about 3 minutes, 10 minutes tops if you count installing the model library. This is not the tightest solution but is still very effective and the simulation is done from measured models on both ends. Our experience is that 10db channel loss budget are pretty standard but this one is 15dB. The simulated TDR of the trace shows an impedance discontinuity that is most likely a via stub that pushes the loss down and out of budget.

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Signal Integrity Tips continues our mini-celebration of the anniversary of IBIS 2.1 ANSI/EIA-656 with this guest post from Michael Mirmak, Chair, IBIS Open Forum. Michael writes:

The year 1995 was certainly one of firsts and achievements. NASDAQ crossed the 1000 mark for the first time. Microsoft released Windows 95. eBay and Yahoo! were founded. The first planet outside our solar system was discovered. And, as Colin kindly noted, IBIS 2.1 was formally approved as a US national standard, ANSI/EIA-656 on December 13th, 1995.

IBIS, the I/O Buffer Information Specification, was by then already a “toddler,” as version 1.0 had been released to the public in June, 1993. It was the answer to a strong industry desire for a non-proprietary behavioral format for buffer signal integrity data that could be shared between EDA tools, system designers and IC vendors alike.

Version 2.1 was revolutionary, with the size of the specification almost tripling due to the added features. The simple ramps used to represent buffer transitions were supplemented with tables of voltage-versus-time data. Support for differential pins, as well as ECL buffer types, was included. Matrix-based package models were added, allowing both true pin- and pad-based analysis using a single buffer model. As a national standard and a practical approach, IBIS 2.1 defined a basic structure which has remained useful ever since.

Much has happened over the intervening 13 years. IBIS 3.2 and 4.0 defined new measurement thresholds, added driver scheduling, improved package support and even created a board description format. IBIS 4.1 and 4.2 brought IBIS together with the analog/mixed-signal world, allowing Verilog-AMS and VHDL-AMS code, as well as Berkeley SPICE elements, to be integrated into the IBIS structure. Now, with the approval of IBIS 5.0 in August of this year, combined power delivery and signal integrity modeling using the simple table-driven IBIS approach becomes a reality. And with the addition of the Algorithmic Modeling Interface (AMI), the specification expands to cover advanced serial-differential equalizer behaviors.

Not a bad list of accomplishments for a teenager.

Happy birthday, IBIS and thanks to its many contributors and users over the years.

- Michael Mirmak
Chair, IBIS Open Forum
http://www.eigroup.org/ibis
http://www.eda.org/ibis

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The IBIS behavioral modeling template emerged as a compromise between the need of chip vendors to protect the intellectual property in their SPICE netlists, and the need of chip consumers to have an “executable datasheet” of the I/O buffers of the chips they design into their systems.

Here’s a snippet from the IBIS home page.

Introduction: IBIS is a standard for electronic behavioral specifications of integrated circuit input/output analog characteristics.

Group Objectives: In order to enable an industry standard method to electronically transport IBIS modeling data between silicon vendors, simulation software vendors, and end customers, this template is proposed. The intention of this template is to specify a consistent format that can be parsed by software, allowing simulation vendors to derive models compatible with their own products.

There are mainy excellent IBIS resources on the web including IBIS Modeling Cookbook (Senior editor: Michael Mirmak)

For a look at how our tool, Agilent ADS, uses the IBIS templates, check out this post entitled Workflow with IBIS Models.

And Happy Birthday, IBIS, from Signal Integrity Tips blog!

MP3 Podcast version of this post

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Abstract

In this webcast, we’ll demonstrate a rapid technique for "what if" analysis for signal integrity applications.

We first automatically fit an ADS circuit model to measured data, using a Tyco XAUI backplane as an illustrative example. Next, the circuit model is used in a series of "what if" simulations to that show what configuration changes will lead to the required performance. Examples include changes to the loss tangent, the via design, and daughter card/backplane trace impedance matching, and combinations of all three. This technique is a much faster and more thorough approach to explore the design space than "iterating the hardware to success."

Who should view this webcast

Signal integrity engineers for multigigabit links who are running into effects previously only seen in RF and microwave circuits.

Date/time

Thursday, January 15th, 2009, 15:00 Central Europe Time, 2PM GMT, 9AM Eastern Standard Time, 8AM Central Standard Time.

Registration

"Back to Basics Redux: Measurement-Based Channel Modeling for Signal Integrity using Agilent ADS"

If you’re a West coasters and don’t want to get up early (6AM), or if you can’t attend live for any other reason, the on-demand version with a recording of the Oct 23rd live Q&A is here: "Back to Basics: Measurement-Based Channel Modeling for Signal Integrity using Agilent ADS"

Also check out the on-demand sister webcast TDR, S-Parameters & Differential Measurements Webcast if you’d like to learn about how the S-parameters, used in my webcast, were measured.

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