Register for “Efficient FPGA Transceiver-based Channel Modeling Using Agilent ADS”.
Free 1-hour live webcast begins 10:00 am PDT 26 June 2008 (1:00 pm EDT, 17:00 GMT)
Sanjeev Gupta (Agilent) and Salman Jiva (Altera)
Abstract
With FPGAs so commonly used in high-speed designs, signal integrity issues can be minimized by properly modeling the signal path. This presentation will model real world circuit boards using S-parameters, showing that it is possible to predict eye opening performance before a system is physically prototyped. Both extracted and measured models for interconnects will be used. A 90nm transceiver model is incorporated in Agilent ADS as a new library element, permitting system level modeling of interconnects and FPGA transceivers. Both measured and modeled results are shown and the correlation is discussed, concluding that the new method is both execution time efficient and is sufficiently accurate to provide a high level of confidence for designers wishing to design serial links to 6.375 Gb/s.
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2 responses so far ↓
1
Free Webcast “Efficient FPGA Transceiver-based Channel Modeling Using Agilent ADS” « Signal Integrity: Back to Basics
// Jun 1, 2008 at 8:26 am
[...] May 28, 2008 · No Comments “Efficient FPGA Transceiver-based Channel Modeling Using Agilent ADS” has moved to out n… [...]
2
Colin Warwick
// Oct 7, 2008 at 12:59 pm
(response to comment on this blog at previous hosting site from Sudhaker “where can i learn more about fpga”)
Hi Sudhakar,
Programming aspects or chip-to-chip SI aspects?
Prof. Bob Stewart and his Steepest Ascent team http://www.steepestascent.com/content/ give excellent FPGA programming classes.
The most popular FPGA programming textbook seems to be the one by Steve Kilts:
http://www.amazon.com/exec/obidos/ASIN/0470054379/309407659003-20
Other websites are
http://www.Xilinx.com
http://www.Altera.com
Wikipedia: http://en.wikipedia.org/wiki/Field-programmable_gate_array
http://www.agilent.com/find/fpga
http://www.fpgacentral.com/
The SI aspects of FPGA design in are similar to other chip-to-chip connections.
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